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MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]
© Motorola Inc., 1981

Original Issue: March 1, 1981
Reprinted: May 1983

Last update: 2024-10-07

Foreword

This is the Programming Manual for the 6809 microprocessor from Motorola Inc. (now Freescale as of 2006).
It is © Motorola Inc., 1981.
It can be freely obtained as a scanned PDF at Freescale's homepage under [Support → ] Documentation → Order Literature (=Literature Distribution Center) → Search for description "6809" and with item status "Active and Archive". Another download location for M6809PM is the BitSavers.org PDF Document Archive, which also has a copy of the original data sheet. PDFs are available at the M6809PM repo of the M6809 Docs team (M6809PM.rev0_May83.pdf, m6809pm.fsl.ad.rev0.pdf) or at Maddes.net.
Sections 1-4 plus appendices A, C, D, E and F got htmlized, so you can easily search inside the text. The original layout of the print was kept wherever possible.
Also some additional errata and corrections were made to the text.
If you think there are any legal concerns to this please contact us via the contact link.
And remember: Use all information at your own risk.

Get all html pages as a zip file from the M6809PM repo of the M6809 Docs team.

Errata & Corrections

Errata (fixing incorrect information) are formatted like this.
Corrections (typos, unambiguousness, readability, etc.) are formatted like this.
HTMLization errors will just be fixed and listed in the change log at the end of this page.

Errata

Corrections

Table Of Contents

PDF pages 5-10

SECTION 1
GENERAL DESCRIPTION
PDF pages 13-24
1.1Introduction
1.2Features
1.3Software Features
1.4Programming Model
1.5Index Registers (X, Y)
1.6Stack Pointer Registers (U, S)
1.7Program Counter (PC)
1.8Accumulator Registers (A, B, D)
1.9Direct Page Register (DP)
1.10Condition Code Register (CC)
1.10.1Condition Code Bits
1.10.1.1Half Carry (H), Bit 5
1.10.1.2Negative (N), Bit 3
1.10.1.3Zero (Z), Bit 2
1.10.1.4Overflow (V), Bit 1
1.10.1.5Carry (C), Bit 0
1.10.2Interrupt Mask Bits and Stacking Indicator
1.10.2.1Fast Interrupt Request Mask (F), Bit 6
1.10.2.2Interrupt Request Mask (I), Bit 4
1.10.2.3Entire Flag (E), Bit 7
1.11Pin Assignments and Signal Description
1.11.1MC6809 Clocks
1.11.1.1Oscillator (EXTAL, XTAL)
1.11.1.2Enable (E)
1.11.1.3Quadrature (Q)
1.11.2MC6809E Clocks (E and Q)
1.11.3Three State Controls (TSC) (MC6809E)
1.11.4Last Instruction Cycle (LIC) (MC6809E)
1.11.5Address Bus (A0-A15)
1.11.6Data Bus (D0-D7)
1.11.7Read/Write (R/W)
1.11.8Processor State Indicators (BA, BS)
1.11.8.1Normal
1.11.8.2Interrupt or Reset Acknowledge
1.11.8.3Sync Acknowledge
1.11.8.4Halt/Bus Grant
1.11.9Reset (RESET)
1.11.10Interrupts
1.11.10.1Non-Maskable Interrupt (NMI)
1.11.10.2Fast Interrupt Request (FIRQ)
1.11.10.3Interrupt Request (IRQ)
1.11.11Memory Read (MRDY) (MC6809)
1.11.12Advanced Valid Memory Address (AVMA) (MC6809E)
1.11.13Halt (HALT)
1.11.14Direct Memory Access/Bus Request (DMA/BREQ) (MC6809)
1.11.15Busy (MC6809E)
1.11.16Power
 
SECTION 2
ADDRESSING MODES
PDF pages 25-30
2.1Introduction
2.2Addressing Modes
2.2.1Inherent
2.2.2Immediate
2.2.3Extended
2.2.4Direct
2.2.5Indexed
2.2.5.1Constant Offset from Register
2.2.5.2Accumulator Offset from Register
2.2.5.3Autoincrement/Decrement from Register
2.2.5.4Indirection
2.2.5.5Extended Indirect
2.2.5.6Program Counter Relative
2.2.6Branch Relative
 
SECTION 3
INTERRUPT CAPABILITIES
PDF pages 31-34
3.1Introduction
3.2Non-Maskable Interrupt (NMI)
3.3Fast Maskable Interrupt Request (FIRQ)
3.4Normal Maskable Interrupt Request (IRQ)
3.5Software Interrupts (SWI, SWI2, SWI3)
 
SECTION 4
PROGRAMMING
PDF pages 35-48
4.1Introduction
4.1.1Position Independence
4.1.2Modular Programming
4.1.2.1Local Storage
4.1.2.2Global Storage
4.1.3Reentrancy/Recursion
4.2M6809 Capabilities
4.2.1Module Construction
4.2.1.1Parameters
4.2.1.2Local Storage
4.2.1.3Global Storage
4.2.2Position-Independent Code
4.2.3Reentrant Programs
4.2.4Recursive Programs
4.2.5Loops
4.2.6Stack Programming
4.2.6.1M6809 Stacking Operations
4.2.6.2Subroutine Linkage
4.2.6.3Software Stacks
4.2.7Real Time Programming
4.3Program Documentation
4.4Instruction Set
 
APPENDIX A
INSTRUCTION SET DETAILS
PDF pages 49-124
A.1Introduction
A.2Notation
Instructions (listed in alphabetical order)
ABX, ADC, ADD (8-Bit), ADD (16-Bit), AND, AND (into CCR), ASL, ASR, BCC, BCS, BEQ, BGE, BGT, BHI, BHS, BIT, BLE, BLO, BLS, BLT, BMI, BNE, BPL, BRA, BRN, BSR, BVC, BVS, CLR, CMP (8-Bit), CMP (16-Bit), COM, CWAI, DAA, DEC, EOR, EXG, INC, JMP, JSR, LD (8-Bit), LD (16-Bit), LEA, LSL, LSR, MUL, NEG, NOP, OR, OR (into CCR), PSHS, PSHU, PULS, PULU, ROL, ROR, RTI, RTS, SBC, SEX, ST (8-Bit), ST (16-Bit), SUB (8-Bit), SUB (16-Bit), SWI, SWI2, SWI3, SYNC, TFR, TST, FIRQ, IRQ, NMI, RESTART
 
APPENDIX B
ASSIST09 MONITOR PROGRAM
PDF pages 125-198
Appendix B will not be htmlized.
 
APPENDIX C
MACHINE CODE TO INSTRUCTION CROSS REFERENCE
PDF pages 199-202
C.1Introduction
 
APPENDIX D
PROGRAMMING AID
PDF pages 203-206
D.1Introduction
 
APPENDIX E
ASCII CHARACTER SET
PDF pages 207-210
E.1Introduction
E.2Character Representation and Code Identification
E.3Control Characters
E.4Graphic Characters
 
APPENDIX F
OPCODE MAP
PDF pages 211-214
F.1Introduction
F.2Opcode Map
 
APPENDIX G
PIN ASSIGNMENTS
PDF pages 215-216
Appendix G will not be htmlized. Same figure as in section 1.11.
 
APPENDIX H
CONVERSION TABLE
PDF pages 217-219
Appendix H will not be htmlized.

List Of Illustrations

PDF page 10

1-1Programming Model
1-2Condition Code Register
1-3Processor Pin Assignments
 
2-1Postbyte Usage for EXG/TFR, PSH/PUL Instructions
 
3-1Interrupt Processing Flowchart
 
4-1Stacking Order
 
B-1Appendix B will not be htmlized.
 
E-1ASCII Character Set
 
G-1Appendix G will not be htmlized. Same figure as in section 1.11.

List Of Tables

PDF pages 11-12

1-1BA/BS Signal Encoding
 
2-1Postbyte Usage for Indexed Addressing Modes
 
3-1Interrupt Vector Locations
 
4-1Instruction Set
4-28-Bit Accumulator and Memory Instructions
4-316-Bit Accumulator and Memory Instructions
4-4Index/Stack Pointer Instructions
4-5Branch Instructions
4-6Miscellaneous Instructions
 
A-1Operation Notation
A-2Register Notation
 
B-1
B-2
B-3		Appendix B will not be htmlized.
 
C-1Machine Code to Instruction Cross Reference
 
D-1Programming Aid
 
E-1Control Characters
E-2Graphic Characters
 
F-1Opcode Map
F-2Indexed Addressing Mode Data
 
H-1
H-2		Appendix H will not be htmlized.

Legal Stuff

PDF page 220

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and Motorola Logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers: (as of 1993 = print of manual)
USA:Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE:Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN:Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.
ASIA PACIFIC:Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

Links

Change log

© Motorola Inc., 1981 (now Freescale as of 2006)
Transformed into HTML by Matthias "Maddes" Bücher in 2006, 2007, 2023.
Maintained by the M6809 Docs team in 2024.
Use all information at your own risk.

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